The present invention relates generally to a digital electronic circuits, and more particularly, to a level shifting flip-flop.
Modern day systems-on-a-chips (SoCs) are designed to consume less power by using lower operating voltages. Multiple voltage domains operating at different voltage supply levels are used to decrease the overall operating voltage of the SoC. These multiple voltage domains require stepping up/down of voltage levels of signals that cross different voltage domains. Level shifter circuits are used to step up/down the logic signal level as it enters a different voltage level domain. Conventionally, a level shifter circuit is coupled to output terminals of a flip-flop, with the level shifter and the flip-flop forming a combination that is used to level shift output signals of the flip-flop.
FIG. 1 shows a schematic diagram of conventional level shifting circuitry 100 that includes a flip-flop 102 and a level shifter circuit 104. The flip-flop 102 receives an input signal (D) at a data input terminal and a clock signal (CP) at a clock input terminal. The flip-flop 102 processes the input signal based on the clock signal and generates output (Q) and inverted output signals (/Q) at output and inverted output terminals, respectively. The Q and /Q output signals are provided to an input terminal of the level-shifter circuit 104. The level shifter circuit 104 shifts the voltage level of the output signal from a first level to a second level to generate a level shifted output signal (Z) at an output terminal of the level shifter circuit 104.
There is a time delay between providing the input signal and obtaining the level-shifted output signal, which includes the time for the flip-flop 102 to generate the output signal Q and the time for the level shifter circuit 104 to generate the level-shifted output signal Z. This circuitry 100 processes the input signal D sequentially. Further, the circuitry 100 has a relatively large size and leads to higher power consumption than other SoC components.
Therefore, it would be advantageous to have a level shifting flip-flop that has low processing time, reduced size and power consumption, and that overcomes the above-mentioned limitations of the conventional circuitry 100.